Flash memory device and manufacture thereof

ABSTRACT

A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. The cavities between neighboring gate structures lower the parasitic capacitance, reduce inter-gate interference, and suppress the influence from writing or erasing operations of nearby memory units.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and benefit of Chinese PatentApplication No. 201610900637.5 filed on Oct. 17, 2016, which isincorporated herein by reference in its entirety.

BACKGROUND (a) Field of the Invention

This inventive concept is related generally to a semiconductortechnology, and more specifically to a flash memory device and itsmanufacturing method.

(b) Description of the Related Art

3D NAND flash memory techniques are progressing rapidly in recent yearsand 3D NAND flash memory based on Terabit Cell Array Transistor (TCAT)is the latest development in this area.

Advancements in manufacturing techniques boost the total number and,accordingly, the total thickness of Oxide-Nitride pairs (O—N pairs) in a3D NAND flash memory. The total thickness of the O—N pairs, however, iscapped by physical limitations of the device, such as maximum allowableheat generated in a working condition. Therefore, to fit in more O—Npairs, the thickness of each individual pair need to be reduced.

In manufacturing a 3D NAND flash memory, the nitride in each O—N pairwill eventually be removed and replaced with metal gate. The remainingoxide in the O—N pair and two neighboring gate structures sandwichingthe oxide form a parasitic capacitance. Reduction in the thickness ofeach individual O—N pair (and hence the thickness of oxide in the O—Npair) results in an increased parasitic capacitance that would have amore prominent adversary effect on the overall performance of thedevice. Hence, a flash memory device with small parasitic capacitanceand inter-gate interference is desirable.

SUMMARY

This inventive concept presents a flash memory device with smallerparasitic capacitance and less inter-gate interference than itsconventional counterparts.

This flash memory device comprises:

a substrate; and

a memory unit on the substrate, comprising:

-   -   a channel structure on the substrate, wherein the channel        structure comprises, in an order from inner to outer of the        channel structure, a channel layer, an insulation layer wrapped        around the channel layer, and a charge capture layer wrapped        around the insulation layer;    -   a plurality of gate structures wrapped around the channel        structure and arranged along an axis of symmetry of the channel        structure, with cavities between neighboring gate structures;    -   a support structure supporting the gate structures; and    -   a plurality of gate contact components each contacting a gate        structure.

Additionally, in the aforementioned device, the support structure maycomprise at least one pillar support component comprising a pillarkernel and a cover layer around the pillar kernel.

Additionally, in the aforementioned device, the pillar kernel may bemade of silicon dioxide and the cover layer may be made of undopedpolycrystalline silicon.

Additionally, in the aforementioned device, the channel structure mayfurther comprise an anti-etching layer wrapped around the side surfacesof the charge capture layer.

Additionally, in the aforementioned device, the anti-etching layer maybe made of a High Temperature Oxide (HTO), wherein the HTO is a siliconoxide formed in a temperature range from 300 to 500 Celsius degree.

Additionally, in the aforementioned device, the channel structure mayfurther comprise a channel kernel surrounded by the channel layer.

Additionally, in the aforementioned device, the memory unit may comprisea plurality of channel structures arranged in the gate structures.

Additionally, in the aforementioned device, each of the gate structuresmay comprise a gate, a work function regulation layer on the surface ofthe gate, and a high-K dielectric layer on the surface of the workfunction regulation layer, wherein a first portion of the high-Kdielectric layer is located between the gate and the channel structureand a second portion of the high-K dielectric layer is located betweenthe gate and the pillar support component.

Additionally, in the aforementioned device, the gate structures may forma staircase pattern, and each of the gate contact components contactsthe gate of a corresponding gate structure at a step of the staircasepattern, and each of the pillar support components is also located on astep of the staircase pattern and separating from the gate contactcomponents.

Additionally, the aforementioned device may further comprising:

a plurality of the memory units separated from each other;

a groove metal filling layer; and

an interval layer, wherein both the groove metal filling layer and theinterval layer are located on the substrate between the neighboringmemory units, and the interval layer separates the groove metal fillinglayer from the gate structures.

Additionally, in the aforementioned device, the substrate further maycomprise a doped region in the substrate contacting the groove metalfilling layer.

Additionally, the aforementioned device may further comprise aninter-layer dielectric layer on the gate structures wrapped around thesupport structure and the gate contact components.

This inventive concept further presents a method for manufacturing aflash memory device, comprising:

providing a substrate;

forming a plurality of first sacrificial layers and a plurality ofsecond sacrificial layers stacked in an alternating manner, wherein thefirst sacrificial layers contain material that is different from thesecond sacrificial layers;

forming a support structure in the first sacrificial layers and thesecond sacrificial layers;

forming a first through-hole exposing an upper surface of the substrateby etching the first sacrificial layers and the second sacrificiallayers;

forming a channel structure in the first through-hole, wherein thechannel structure comprises, in an order from inner to outer of thechannel structure, a channel layer, an insulation layer wrapped aroundthe channel layer, and a charge capture layer wrapped around theinsulation layer;

forming a plurality of first cavities by removing the first sacrificiallayers;

forming a plurality of gate structures in the first cavities;

forming a plurality of second cavities between neighboring gatestructures by removing the second sacrificial layers; and

forming a plurality of gate contact components each connecting to a gatestructure.

Additionally, in the aforementioned method, the support structure maycomprise at least one pillar support component, and the pillar supportcomponent comprises a pillar kernel and a common cover layer wrappedaround the pillar kernel.

Additionally, in the aforementioned method, the first sacrificial layersand the second sacrificial layers may form a staircase pattern, andforming a support structure in the first sacrificial layers and thesecond sacrificial layers comprises:

-   -   forming a first dielectric layer on the staircase pattern        comprising the first sacrificial layers and the second        sacrificial layers;    -   forming an opening exposing the upper surface of the substrate        by etching the first dielectric layer, the first sacrificial        layers and the second sacrificial layers;    -   forming the pillar support component in the opening; and    -   forming a second dielectric layer covering the pillar support        component on the first dielectric layer.

Additionally, in the aforementioned method, forming the pillar supportcomponent in the opening may comprise:

forming a first cover layer on a side surface and the bottom of theopening;

forming the pillar kernel filling the opening on the first cover layer;

forming a pillar cavity by etching back a portion of the pillar kernel;and

forming a second cover layer filling the pillar cavity, wherein thefirst cover layer and the second cover layer form the common cover layerwrapped around the pillar kernel.

Additionally, in the aforementioned method, the pillar kernel may bemade of silicon dioxide and the common cover layer may be made ofundoped polycrystalline silicon.

Additionally, in the aforementioned method, the first sacrificial layersmay be made of silicon nitride and the second sacrificial layers may bemade of silicon dioxide.

Additionally, in the aforementioned method, the channel structurefurther may comprise an anti-etching layer wrapped around the chargecapture layer.

Additionally, in the aforementioned method, the anti-etching layer maybe made of a High Temperature Oxide (HTO), wherein the HTO is a siliconoxide formed in a temperature range from 300 to 500 Celsius degree.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings describe some embodiments of this inventive concept andwill be used to describe this inventive concept together with thespecification.

FIG. 1 shows a flowchart illustrating a flash memory manufacturingmethod in accordance with one or more embodiments of this inventiveconcept.

FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11A, 11B, 12A, 12B, 13A, 13B, 14, 15,16, 17, 18A, 18B, 19, 20, 21, 22, 23A, 23B, 24A, 24B, 25A, 25B, 26A, and26B show schematic cross-sectional views illustrating different stagesof a flash memory manufacturing method in accordance with one or moreembodiments of this inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Example embodiments of the inventive concept are described withreference to the accompanying drawings. As those skilled in the artwould realize, the described embodiments may be modified in various wayswithout departing from the spirit or scope of the inventive concept.Embodiments may be practiced without some or all of these specifieddetails. Well known process steps and/or structures may not be describedin detail, in the interest of clarity.

The drawings and descriptions are illustrative and not restrictive. Likereference numerals may designate like (e.g., analogous or identical)elements in the specification. To the extent possible, any repetitivedescription will be minimized.

Relative sizes and thicknesses of elements shown in the drawings arechosen to facilitate description and understanding, without limiting theinventive concept. In the drawings, the thicknesses of some layers,films, panels, regions, etc., may be exaggerated for clarity.

Embodiments in the figures may represent idealized illustrations.Variations from the shapes illustrated may be possible, for example dueto manufacturing techniques and/or tolerances. Thus, the exampleembodiments shall not be construed as limited to the shapes or regionsillustrated herein but are to include deviations in the shapes. Forexample, an etched region illustrated as a rectangle may have rounded orcurved features. The shapes and regions illustrated in the figures areillustrative and shall not limit the scope of the embodiments.

Although the terms “first,” “second,” etc. may be used herein todescribe various elements, these elements shall not be limited by theseterms. These terms may be used to distinguish one element from anotherelement. Thus, a first element discussed below may be termed a secondelement without departing from the teachings of the present inventiveconcept. The description of an element as a “first” element may notrequire or imply the presence of a second element or other elements. Theterms “first,” “second,” etc. may also be used herein to differentiatedifferent categories or sets of elements. For conciseness, the terms“first,” “second,” etc. may represent “first-category (or first-set),”“second-category (or second-set),” etc., respectively.

If a first element (such as a layer, film, region, or substrate) isreferred to as being “on,” “neighboring,” “connected to,” or “coupledwith” a second element, then the first element can be directly on,directly neighboring, directly connected to or directly coupled with thesecond element, or an intervening element may also be present betweenthe first element and the second element. If a first element is referredto as being “directly on,” “directly neighboring,” “directly connectedto,” or “directly coupled with” a second element, then no intendedintervening element (except environmental elements such as air) may alsobe present between the first element and the second element.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like, may be used herein for ease of description todescribe one element or feature's spatial relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms may encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device may be otherwise oriented (rotated 90degrees or at other orientation), and the spatially relative descriptorsused herein shall be interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments and is not intended to limit the inventive concept. As usedherein, singular forms, “a,” “an,” and “the” may indicate plural formsas well, unless the context clearly indicates otherwise. The terms“includes” and/or “including,” when used in this specification, mayspecify the presence of stated features, integers, steps, operations,elements, and/or components, but may not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups. Unless otherwise defined, terms(including technical and scientific terms) used herein have the samemeanings as what is commonly understood by one of ordinary skill in theart related to this field. Terms, such as those defined in commonly useddictionaries, shall be interpreted as having meanings that areconsistent with their meanings in the context of the relevant art andshall not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

The term “connect” may mean “electrically connect.” The term “insulate”may mean “electrically insulate.”

Unless explicitly described to the contrary, the word “comprise” andvariations such as “comprises,” “comprising,” “include,” or “including”may imply the inclusion of stated elements but not the exclusion ofother elements.

Various embodiments, including methods and techniques, are described inthis disclosure. Embodiments of the inventive concept may also cover anarticle of manufacture that includes a non-transitory computer readablemedium on which computer-readable instructions for carrying outembodiments of the inventive technique are stored. The computer readablemedium may include, for example, semiconductor, magnetic, opto-magnetic,optical, or other forms of computer readable medium for storing computerreadable code. Further, the inventive concept may also cover apparatusesfor practicing embodiments of the inventive concept. Such apparatus mayinclude circuits, dedicated and/or programmable, to carry out operationspertaining to embodiments of the inventive concept. Examples of suchapparatus include a general purpose computer and/or a dedicatedcomputing device when appropriately programmed and may include acombination of a computer/computing device and dedicated/programmablehardware circuits (such as electrical, mechanical, and/or opticalcircuits) adapted for the various operations pertaining to embodimentsof the inventive concept.

FIG. 1 shows a flowchart illustrating a flash memory manufacturingmethod in accordance with one or more embodiments of this inventiveconcept.

In step S101, provide a substrate.

In step S102, form a plurality of first sacrificial layers and aplurality of second sacrificial layers stacking over each otheralternately on the substrate, wherein the first sacrificial layers aredifferent from the second sacrificial layers. For example, the firstsacrificial layers may be made of silicon nitride and the secondsacrificial layers may be made of silicon dioxide.

In step S103, form a support structure in the first sacrificial layersand the second sacrificial layers. In one embodiment, the supportstructure may comprise at least one pillar support component comprisinga pillar kernel and a cover layer wrapped around the pillar kernel. Thepillar kernel may be made of silicon dioxide and the cover layer may bemade of polycrystalline silicon, such as undoped polycrystallinesilicon. The cover layer protects the pillar kernel from being damagedduring the succeeding etching process to remove the second sacrificiallayers.

In step S104, form a first through-hole exposing an upper surface of thesubstrate by etching the first sacrificial layers and the secondsacrificial layers.

In step S105, form a channel structure in the first through-hole,wherein the channel structure comprises, in an order from inner to outerof the channel structure, a channel layer, an insulation layer (workingas a tunnel insulation layer) wrapped around the channel layer, and acharge capture layer wrapped around the insulation layer.

As an example, the channel layer may be made of polycrystalline silicon,the insulation layer may be made of a silicon oxide, and the chargecapture layer may be made of silicon nitride. Optionally, the channelstructure may further comprise a channel kernel being wrapped around bythe channel layer. The channel kernel may be made of silicon dioxide.The composition materials for various layers of the channel structureare demonstrative and are not intended to limit the scope of thisinventive concept.

In step S106, form a plurality of first cavities by removing the firstsacrificial layers.

In step S107, form a plurality of gate structures in the first cavities.Each of the gate structures may comprise a gate, a work functionregulation layer on the surface of the gate, and a high-K dielectriclayer on the surface of the work function regulation layer. A firstportion of the high-K dielectric layer is located between the gate andthe channel structure, and a second portion of the high-K dielectriclayer is located between the gate and the pillar support component.

In step S108, form a plurality of second cavities between neighboringgate structures by removing the second sacrificial layers. The secondsacrificial layers may be removed by an etching process.

In step S109, form a plurality of gate contact components eachcontacting a gate structure.

In this manufacturing method, the second cavities are formed betweenneighboring gate structures by removing the second sacrificial layers,these cavities lower the parasitic capacitance, reduce inter-gateinterference, and reduce any unintended effect from writing or erasingoperations of nearby memory units.

As an example, due to a smaller dielectric constant of air than silicondioxide, a 3D NAND flash memory device with the second cavities filledwith air has a smaller parasitic capacitance than those of itsconventional counterparts.

Additionally, the support structure formed in this manufacturing methodprovides structural reinforcement to the gate structures, which may beweakened by the second cavities, and prevents them from collapsing.

In one embodiment, the channel structure may further comprise ananti-etching layer wrapped around the charge capture layer. Optimally,the anti-etching layer may be made of a High Temperature Oxide (HTO). Asan example, the HTO may be a silicon oxide formed in a temperature rangefrom 300 to 500 Celsius degree (e.g. 400 Celsius degree). Compared toTetraethyl Orthosilicate (TEOS), HTO has higher compactness and canbetter resist the etching processes, such as a dry etching like plasmaetching or a wet etching process, that will be conducted to remove thesecond sacrificial layers. Therefore, HTO provides a better protectionto the charge capture layer than TEOS.

FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11A, 11B, 12A, 12B, 13A, 13B, 14, 15,16, 17, 18A, 18B, 19, 20, 21, 22, 23A, 23B, 24A, 24B, 25A, 25B, 26A, and26B show schematic cross-sectional views illustrating different stagesof a flash memory manufacturing method in accordance with one or moreembodiments of this inventive concept. Referring to these drawings, thisflash memory manufacturing method will be described in details below.

First, referring to FIG. 2, a substrate 200, which may be a siliconsubstrate, is provided.

Then, a plurality of first sacrificial layers 201 and a plurality ofsecond sacrificial layers 202 are formed on the substrate 200, with thefirst sacrificial layers 201 and the second sacrificial layers 202stacked in alternating layers. Referring to FIG. 2, a first sacrificiallayer 201 may first be deposited on the substrate 200, followed by asecond sacrificial layer 202, and followed by another first sacrificiallayer 201, and so on. The first sacrificial layers 201 and the secondsacrificial layers 202 may be made of different materials. For example,the first sacrificial layer 201 may be made of silicon nitride and thesecond sacrificial layers 202 may be made of silicon dioxide.

Referring to FIG. 3, a staircase pattern is formed by etching the firstsacrificial layers 201 and the second sacrificial layers 202.

It is understood that, for conciseness, FIG. 3 and other drawings mayonly show a portion of the entire cross-sectional view of the device inthis inventive concept. For example, FIG. 3 may only show a portion ofthe staircase pattern that includes the first sacrificial layers 201 andthe second sacrificial layers 202. The views of these drawings are notintended to limit the scope of this inventive concept.

Then, a support structure is formed in the first sacrificial layers 201and the second sacrificial layers 202, a process to form the supportstructure will be described below in reference to FIGS. 4, 5, 6, 7, 8,9, 10, 11A, and 11B.

Referring to FIG. 4, a first dielectric layer 203 is formed on thestaircase pattern comprising the first sacrificial layers 201 and thesecond sacrificial layers 202. The first dielectric layer 203 may bemade of silicon dioxide.

Then, an opening 206 exposing a portion of the upper surface of thesubstrate 200 is formed by etching the first dielectric layer 203, thefirst sacrificial layers 201 and the second sacrificial layers 202.Referring to FIG. 4, a patterned hard mask layer 205, which may be aphotoresist layer, may first be formed on the first dielectric layer203, then the opening 206 exposing a portion of the upper surface of thesubstrate 200 may be formed by etching the first dielectric layer 203,the first sacrificial layers 201 and the second sacrificial layers 202using the hard mask layer 205 as a mask. After that, the hard mask layer205 may be removed and a structure as shown in FIG. 5 results.

Then, a pillar support component is formed in the opening 206.

Referring to FIG. 6, a process to form a pillar support component in theopening 206 may comprise: depositing a first cover layer 211 on a sidesurface and the bottom of the opening 206, wherein the first cover layer211 may be made of polycrystalline silicon such as undopednanopolycrystalline silicon; and forming a pillar kernel 212 filling theopening 206 on the first cover layer 211, wherein the pillar kernel 212may be made of silicon dioxide.

Referring to FIG. 7, optionally, the process to form a pillar supportcomponent in the opening 206 may further comprise: forming a pillarcavity 213 by etching back a portion of the pillar kernel 212.

Referring to FIG. 8, optionally, the process to form a pillar supportcomponent in the opening 206 may further comprise: depositing a secondcover layer 214 filling the pillar cavity 213. The second cover layer214 may be made of the same material as the first cover layer 211. Thefirst cover layer 211 and the second cover layer 214 wrap the pillarkernel 212. For convenience of this description, the first cover layer211 and the second cover layer 214 together will be marked as a commoncover layer 215 starting from FIG. 9.

Referring to FIG. 10, optionally, the process to form a pillar supportcomponent in the opening 206 may further comprise: forming the pillarsupport component 210 by removing a portion of the common cover layer215 on the first dielectric layer 203.

Referring to FIGS. 11A and 11B, after the pillar support component 210is formed, a second dielectric layer 303 covering the pillar supportcomponent 210 is formed on the first dielectric layer 203. The seconddielectric layer 303 may be made of silicon dioxide. Optionally, aplanarization process, such as a Chemical Mechanical Planarization (CMP)process, may be conducted on the second dielectric layer 303. Here, FIG.11B shows a cross-sectional view of the same structure of FIG. 11A on across-plane perpendicular to the paper and goes through line A-A′ inFIG. 11A, and viewed along an arrow direction shown in FIG. 11A.

For convenience of this description, the first dielectric layer 203 andthe second dielectric layer 204 together will be marked as a commondielectric layer 403 starting from FIG. 11B. This concludes the processto form a support structure in the first sacrificial layers 201 and thesecond sacrificial layers 202. As shown in those drawings, a pluralityof pillar support components 210 may be formed, this description focuson the process to form only one pillar support component 210 with anunderstanding that other pillar support components may be formed by thesame process. Three pillar support components 210 are exemplarilydisplayed in FIG. 11A, it should be understood that the exact number ofpillar support components may vary depending on actual requirements andis not limited herein.

Referring to FIG. 12A, a first through-hole 220 exposing the uppersurface of the substrate 200 is formed by etching the first sacrificiallayers 201 and the second sacrificial layers 202. If the commondielectric layer 403 has been formed in preceding stages, forming afirst through-hole 220 also comprises etching the common dielectriclayer 403.

FIG. 12B shows a cross-sectional view of the same structure of FIG. 12Aon a cross-plane perpendicular to the paper and goes through line B-B′in FIG. 12A, and viewed along an arrow direction shown in FIG. 12A.Referring to FIG. 12B, in one embodiment, a plurality of firstthrough-holes 220 may be formed and these first through-holes 220 may bearranged staggeringly. FIG. 12A shows a cross-sectional view of the samestructure of FIG. 12B on a cross-plane perpendicular to the paper andgoes through line C-C′ in FIG. 12B, and viewed along an arrow directionshown in FIG. 12B. FIG. 12A only shows two first through-holes 220 onthe bottom of FIG. 12B, but not two first through-holes 220 on the topof FIG. 12B. It should be understood that the number of the firstthrough-holes 220 in FIGS. 12A and 12B is exemplary and is not intendedto limit the scope of this inventive concept.

Referring to FIGS. 13A and 13B, a channel structure 230 is formed in thefirst through-hole 220. The process to form a channel structure 230 maycomprise: epitaxially growing an epitaxy component 221 on the bottom ofthe first through-hole 220; and forming the channel structure 230 on theepitaxy component 221. As an example, this process may comprise:depositing an anti-etching layer 234 on a side surface and the bottom ofthe first through-hole 220, wherein the anti-etching layer 234 is alsoon the epitaxy component 221 and may be made of an HTO; depositing acharge capture layer 233 on the anti-etching layer 234; and depositingan insulation layer 232 on the charge capture layer 233. Referring toFIG. 13A, optionally, a portion of the insulation layer 232, a portionof the charge capture layer 233, a portion of the anti-etching layer 234on the epitaxy component 221, and a portion of the epitaxy component 221may be etched away to form an epitaxy cavity in the epitaxy component221, then a channel layer 231 may be deposited on the epitaxy component221 and on a side surface of the insulation layer 232. Optionally, achannel kernel 235 filling the first through-hole 220 may be formed onthe channel layer 231. The channel kernel 235, the channel layer 231,the insulation layer 232, the charge capture layer 233, and theanti-etching layer 234 form the channel structure 230.

Referring to FIG. 13B, in one embodiment, each of the firstthrough-holes may have a channel structure 230 formed in it, so thatthere would be a plurality of channel structures 230 formed in the firstsacrificial layers 201 and the second sacrificial layers 202, thesechannel structures 230 may be arranged staggeringly, as shown in FIG.13B.

Referring to FIG. 14, optionally, the process to form a channelstructure 230 may further comprise: etching back the channel kernel 235to form a kernel cavity 236.

Referring to FIG. 15, optionally, the process to form a channelstructure 230 may further comprise: depositing the channel layer 231filling the kernel cavity 236 so that the channel layer 231 is on thechannel kernel 235.

Referring to FIG. 16, optionally, the process to form a channelstructure 230 may further comprise: removing a portion of the channellayer 231 on the common dielectric layer 403 to form the channelstructure 230 as shown in FIG. 16. Optimally, in the channel structure230 of FIG. 16, the channel layer 231 also covers an upper surface ofthe channel kernel 235, which makes it easy to form a channel contactcomponent connecting to the channel layer in the succeeding stages.

Referring to FIG. 17, optionally, a third dielectric layer 503 coveringthe channel structure 230 may be deposited on the common dielectriclayer 403.

Referring to FIGS. 18A and 18B, after the channel structure 230 isformed, a groove 240 exposing the upper surface of the substrate 200 isformed by etching the first sacrificial layers 201 and the secondsacrificial layers 202. FIG. 18B shows a cross-sectional view of thesame structure of FIG. 18A on a cross-plane perpendicular to the paperand goes through line E-E′ in FIG. 18A, and viewed along an arrowdirection shown in FIG. 18A. If the common dielectric layer 403(comprising the first dielectric layer 203 and the second dielectriclayer 303) and the third dielectric layer 503 have been formed inpreceding stages, forming a groove 240 further comprises etching thecommon dielectric layer 403 and the third dielectric layer 503.Referring to FIG. 18A, a doped region 241 is formed in the substrate 200by doping a portion of the substrate 200 at the bottom of the groove240, the doped region 241 may work as a source electrode or a drainelectrode. The doping process may be conducted by ion implantation, andthe doped region 241 may be an N-type doped region.

Referring to FIG. 19, a plurality of first cavities 251 are formed byremoving the first sacrificial layers 201.

Referring to FIG. 20, a plurality of gate structures 260 are formed inthe first cavities 251. Each of the gate structures 260 may comprise agate 261, a work function regulation layer 262 on the surface of thegate 261, and a high-K dielectric layer 263 on the surface of the workfunction regulation layer 262. The gate 261 may be made of a metallicmaterial such as tungsten, the work function regulation layer 262 may bemade of titanium nitride (TiN), and the high-K dielectric layer 263 maybe made of hafnium oxide (HfO₂).

Referring to FIG. 20, in one embodiment, forming gate structures 260 inthe first cavities 251 comprises: forming gate structures 260 in thefirst cavities 251 and the groove 240. Referring to FIG. 21, optionally,forming gate structures 260 in the first cavities 251 may furthercomprise: removing the gate structures 260 in the groove 240.

Referring to FIG. 22, after the gate structures 260 in the groove 240have been removed, an interval layer 271 is formed on a side surface ofthe groove 240. After the interval layer 271 has been formed, a groovemetal filling layer 272 filling the groove 240 and contacting the dopedregion 241 is formed on the substrate 200. In this embodiment, theinterval layer 271 separates the groove metal filling layer 272 from thegate structures 260, and may be made of a silicon oxide that has ahigher compactness than the material used for the second sacrificiallayers 202.

Referring to FIGS. 23A and 23B, a plurality of second cavities 252 areformed between neighboring gate structures 260 by removing the secondsacrificial layers 202 with a dry etching or a wet etching process. Theetching process used in this step has a slower removal rate to HTO thanto the second sacrificial layers 202, hence the anti-etching layer 234comprising HTO can protect various layers of the channels structure 230,such as the charge capture layer 233, from being damaged during thisetching process.

Here, FIG. 23B shows a cross-sectional view of the same structure ofFIG. 23A on a cross-plane perpendicular to the paper and goes throughline F-F′ in FIG. 23A, and viewed along an arrow direction shown in FIG.23A. Referring to FIG. 23B, the gate structures 260 may form a staircasepattern. When removing the second sacrificial layers 202, the commondielectric layer 403 (comprising the first dielectric layer 203 and thesecond dielectric layer 303) and the third dielectric layer 503 willalso be removed. The support structure, including a plurality of pillarsupport components 210, will provide structural reinforcement to thegate structures 260 and prevent them from collapsing after these layersare removed.

In some embodiments, the interval layer 271 may have a highercompactness than the second sacrificial layers 202, the commondielectric layer 403, and the third dielectric layer 503. Hence, with aproper etching process, the interval layer 271 may remain intact whenthe second sacrificial layers 202, the common dielectric layer 403 andthe third dielectric layer 503 are removed.

Referring to FIGS. 24A, 24B, 25A, 25B, 26A, and 26B, a process to formgate contact components will be described below.

Referring to FIGS. 24A and 24B, in one embodiment, forming gate contactcomponents may comprise: forming an inter-layer dielectric layer 603wrapped around the support structure on the gate structures 260. Theinter-layer dielectric layer 603 may be made of silicon dioxide. FIG.24B shows a cross-sectional view of the same structure of FIG. 24A on across-plane perpendicular to the paper and goes through line G-G′ inFIG. 24A, and viewed along an arrow direction shown in FIG. 24A.

Referring to FIG. 25B, forming gate contact components may furthercomprise: forming second through-holes 281 exposing the gate structures260 by etching the inter-layer dielectric layer 603. The secondthrough-holes 281 may expose the gate 261 of the gate structures 260.Referring to FIG. 25A, in one embodiment, a third through-hole 282exposing the channel layer 231 and a fourth through-hole 283 exposingthe groove metal filling layer 272 may also be formed. FIG. 25B shows across-sectional view of the same structure of FIG. 25A on a cross-planeperpendicular to the paper and goes through line H-H′ in FIG. 25A, andviewed along an arrow direction shown in FIG. 25A.

Since FIGS. 24B and 25B are cross-sectional views observed on differentcross-planes, the pillar support components 210 shown on FIG. 24B arenot displayed on FIG. 25B. These drawings are example views only. Insome embodiments, the second through-holes 281 connecting to thestaircase pattern may be formed in a location so that it will bedisplayed in FIG. 24B, together with the pillar support components 210.Since the width of each step of the staircase pattern is relativelylarge (around 500 nm), there is room for sufficient separation betweensecond through-holes 281 and the pillar support components 210.

Referring to FIG. 26B, forming gate contact components may furthercomprise forming a gate contact component 291 in each of the secondthrough-holes 281. The gate contact components 291 may be made of ametallic material such as copper or tungsten. Referring to FIG. 26B, inone embodiment, the gate structures 260 form a staircase pattern andeach of the gate contact components 291 contacts the gate 261 of acorresponding gate structure 260 at a step of the staircase pattern. Inone embodiment, each of the pillar support components 210 is alsolocated on a step of the staircase pattern and separating from the gatecontact components 291. FIG. 26B shows a cross-sectional view of thesame structure of FIG. 26A on a cross-plane perpendicular to the paperand goes through line I-I′ in FIG. 26A, and viewed along an arrowdirection shown in FIG. 26A.

Referring to FIG. 26A, in one embodiment, when forming gate contactcomponents, a channel contact component 292 may be formed in the thirdthrough-hole 282 and a groove contact component 293 may be formed in thefourth through-hole 283. The channel contact component 292 and thegroove contact component 293 may be made of a metallic material such ascopper or tungsten.

This concludes the description of the above description pertains to aflash memory manufacturing method in accordance with one or moreembodiments of this inventive concept.

This inventive concept further presents a flash memory device. Thisflash memory device will be described below in reference to FIGS. 24B,26A, and 26B.

Referring to FIG. 26A, this flash memory device comprises a substrate200 and a memory unit on the substrate 200. The embodiment of FIG. 26Ashows two memory units, annotated as a first memory unit 310 and asecond memory unit 320. The exact number of memory units in a flashmemory device may vary depending on actual requirements and is notlimited herein. Since the two memory units have similar structures, thedescription will focus on the first memory unit 310 only.

Referring to FIG. 26A, the memory unit, such as the first memory unit310, may comprise a channel structure 230 on the substrate 200. Thechannel structure 230 comprises, in an order from inner to outer of thechannel structure, a channel layer 231, an insulation layer 232 wrappedaround the channel layer 231, and a charge capture layer 233 wrappedaround the insulation layer 232. In one embodiment, the channelstructure 230 may further include an anti-etching layer 234 wrappedaround the charge capture layer 233. The anti-etching layer 234 may bemade of a HTO. As an example, this HTO may be a silicon oxide formed ina temperature range from 300 to 500 Celsius degree (e.g. 400 Celsiusdegree). In one embodiment, the channel structure 230 may furthercomprise a channel kernel 234 surrounded by the channel layer 231. Thechannel kernel 234 may be made of silicon dioxide. In one embodiment,the memory unit may comprise a plurality of channel structures arrangedin gate structures.

In one embodiment, the insulation layer 232 and the charge capture layer233 may completely wrap around the surfaces of the channel layer 231that is perpendicular to the top surface of the substrate 200. Inanother embodiment, the insulation layer 232 and the charge capturelayer 233 may partially wrap around those surfaces of the channel layer231.

Referring to FIG. 26A, the memory unit, such as the first memory unit310, may further comprise a plurality of gate structures 260 wrappedaround the channel structure 230 and arranged along an axis of symmetrythat extends through the channel structure 230, and a plurality ofcavities 252 (the second cavities in previous description) betweenneighboring gate structures 260. The axis of symmetry of the channelstructure 230 is an axis along which the channel structure 230 extends,which is also a direction along which a work current flows in thechannel layer 231 when powered on. As an example, in some embodiments,the axis of symmetry of the channel structure 230 is substantiallyperpendicular to an upper surface of the substrate 200. In oneembodiment, each of the gate structures 260 may comprise: a gate 261, awork function regulation layer 262 on the surface of the gate 261, and ahigh-K dielectric layer 263 on the surface of the work functionregulation layer 262. A first portion of the high-K dielectric layer 263is located between the gate 261 and the channel structure 230, and asecond portion of the high-K dielectric layer 263 is located between thegate 361 and pillar support components 210, as shown in FIG. 24B. Theexact number of the gate structures 360 may vary depending on actualrequirements and is not limited herein. As an example, the number may beany number between 32 and 128.

Referring to FIG. 24B, the memory unit, such as the first memory unit310, may further comprise a support structure supporting the gatestructures 260. As an example, the support structure may comprise atleast one pillar support component 210. The pillar support component 210may comprise a pillar kernel 212 and a common cover layer 215 wrappedaround the pillar kernel 212. The pillar kernel 212 may be made ofsilicon dioxide and the common cover layer 215 may be made of undopedpolycrystalline silicon. The support structure may be located on eitherthe middle or the edge of the entire structure comprising the memoryunit.

Referring to FIG. 26B, the memory unit, such as the first memory unit310, may further comprise a plurality of gate contact components 291each connecting to one gate structure 260. As an example, the gatecontact component 291 may contact the gate 261 of the corresponding gatestructure 260. Referring to FIG. 26B, in one embodiment, the gatestructures 260 form a staircase pattern, and each of the gate contactcomponents 291 contacts the gate 261 of a corresponding gate structure260 at a step of the staircase pattern. Referring to FIG. 24B, thepillar support component 210 may also locate at a step of the staircasepattern and separating from the gate contact components 291.

Referring to FIG. 26A, in one embodiment, the memory unit, such as thefirst memory unit 310, may further comprise a channel contact component292 connecting to the channel layer 231.

Referring to FIG. 26A, in one embodiment, the flash memory device ofthis inventive concept may comprise a plurality of memory unitsseparated from each other. A groove metal filling layer 272 and aninterval layer 271 may be formed between neighboring memory units on thesubstrate 200, wherein the interval layer 271 separating the groovemetal filling layer 272 from the gate structures 260.

Referring to FIG. 26A, in one embodiment, the substrate 200 may comprisea doped region 241 in the substrate 200 contacting the groove metalfilling layer 272.

Referring to FIG. 26A, in one embodiment, the flash memory device ofthis inventive concept may further comprise a groove contact component293 connecting to the groove metal filling layer 272.

Referring to FIGS. 24B and 26B, the flash memory device of thisinventive concept may further comprise an inter-layer dielectric layer603 around the support structure and the gate contact components 291 onthe gate structures 260. Referring to FIG. 26A, the inter-layerdielectric layer 603 may also wrap the groove contact component 293 andthe channel contact component 292.

In one embodiment, the flash memory device of this inventive concept mayfurther comprise an epitaxy component 221 on the substrate 200, whereinthe channel structure 230 is on the epitaxy component 221.

The working mechanism of the flash memory device of this inventiveconcept is similar to that of a conventional 3D NAND flash memory andwill be briefly described below. To write a data into the flash memory,one of the groove contact component 293 and the channel contactcomponent 292 is grounded, with the other connecting to a positivevoltage source, which results in a working current flowing in thechannel layer 231 of the channel structure 230. At this time, if a gatevoltage is applied to a gate structure wrapped around the channelstructure 230, the charge carriers, such as electrons, will tunnelthrough the insulation layer and reach the charge capture layer torealize data writing.

In the flash memory device of this inventive concept, the cavities inneighboring gate structures lower the parasitic capacitance, reduceinter-gate interference, and suppress the influence from writing orerasing operations of nearby memory units.

As an example, due to a smaller dielectric constant of air than silicondioxide, a 3D NAND flash memory device with the cavities filled with airhas a smaller parasitic capacitance than those of its conventionalcounterparts.

Additionally, the support structure formed in this flash memory deviceprovides structural reinforcement to the gate structures, which may beweakened by the cavities, and prevents them from collapsing.

This above description pertains to a flash memory device in accordancewith one or more embodiments of this inventive concept.

While this inventive concept has been described in terms of severalembodiments, there are alterations, permutations, and equivalents, whichfall within the scope of this disclosure. It shall also be noted thatthere are alternative ways of implementing the methods and apparatusesof the inventive concept. Furthermore, embodiments may find utility inother applications. The abstract section is provided herein forconvenience and, due to word count limitation, is accordingly writtenfor reading convenience and shall not be employed to limit the scope ofthe claims. It is therefore intended that the claims be interpreted asincluding all such alterations, permutations, and equivalents.

What is claimed is:
 1. A flash memory device, comprising: a substrate;and a memory unit on the substrate, comprising: a channel structure onthe substrate, wherein the channel structure comprises, in an order frominner to outer of the channel structure, a channel layer, an insulationlayer wrapped around the channel layer, and a charge capture layerwrapped around the insulation layer; a plurality of gate structureswrapped around the channel structure and arranged along an axis ofsymmetry of the channel structure, with cavities between neighboringgate structures; a support structure supporting the gate structures; anda plurality of gate contact components each contacting a gate structure.2. The device of claim 1, wherein the support structure comprises atleast one pillar support component comprising a pillar kernel and acover layer around the pillar kernel.
 3. The device of claim 2, whereinthe pillar kernel is made of silicon dioxide and the cover layer is madeof undoped polycrystalline silicon.
 4. The device of claim 1, whereinthe channel structure further comprises an anti-etching layer wrappedaround the side surfaces of the charge capture layer.
 5. The device ofclaim 4, wherein the anti-etching layer is made of a High TemperatureOxide (HTO), wherein the HTO is a silicon oxide formed in a temperaturerange from 300 to 500 Celsius degree.
 6. The device of claim 1, whereinthe channel structure further comprises a channel kernel surrounded bythe channel layer.
 7. The device of claim 1, wherein the memory unitcomprises a plurality of channel structures arranged in the gatestructures.
 8. The device of claim 2, wherein each of the gatestructures comprises a gate, a work function regulation layer on thesurface of the gate, and a high-K dielectric layer on the surface of thework function regulation layer, wherein a first portion of the high-Kdielectric layer is located between the gate and the channel structureand a second portion of the high-K dielectric layer is located betweenthe gate and the pillar support component.
 9. The device of claim 8,wherein the gate structures form a staircase pattern, and wherein eachof the gate contact components contacts the gate of a corresponding gatestructure at a step of the staircase pattern, and each of the pillarsupport components is also located on a step of the staircase patternand separating from the gate contact components.
 10. The device of claim1, further comprising: a plurality of the memory units separated fromeach other; a groove metal filling layer; and an interval layer, whereinboth the groove metal filling layer and the interval layer are locatedon the substrate between the neighboring memory units, and the intervallayer separates the groove metal filling layer from the gate structures.11. The device of claim 10, wherein the substrate further comprises adoped region in the substrate contacting the groove metal filling layer.12. The device of claim 1, further comprises an inter-layer dielectriclayer on the gate structures wrapped around the support structure andthe gate contact components.
 13. A method for manufacturing a flashmemory device, comprising: providing a substrate; forming a plurality offirst sacrificial layers and a plurality of second sacrificial layersstacked in an alternating manner, wherein the first sacrificial layerscontain material that is different from the second sacrificial layers;forming a support structure in the first sacrificial layers and thesecond sacrificial layers; forming a first through-hole exposing anupper surface of the substrate by etching the first sacrificial layersand the second sacrificial layers; forming a channel structure in thefirst through-hole, wherein the channel structure comprises, in an orderfrom inner to outer of the channel structure, a channel layer, aninsulation layer wrapped around the channel layer, and a charge capturelayer wrapped around the insulation layer; forming a plurality of firstcavities by removing the first sacrificial layers; forming a pluralityof gate structures in the first cavities; forming a plurality of secondcavities between neighboring gate structures by removing the secondsacrificial layers; and forming a plurality of gate contact componentseach connecting to a gate structure.
 14. The method of claim 13, whereinthe support structure comprises at least one pillar support component,wherein the pillar support component comprises a pillar kernel and acommon cover layer wrapped around the pillar kernel.
 15. The method ofclaim 14, wherein the first sacrificial layers and the secondsacrificial layers form a staircase pattern, and wherein forming asupport structure in the first sacrificial layers and the secondsacrificial layers comprises: forming a first dielectric layer on thestaircase pattern comprising the first sacrificial layers and the secondsacrificial layers; forming an opening exposing the upper surface of thesubstrate by etching the first dielectric layer, the first sacrificiallayers and the second sacrificial layers; forming the pillar supportcomponent in the opening; and forming a second dielectric layer coveringthe pillar support component on the first dielectric layer.
 16. Themethod of claim 15, wherein forming the pillar support component in theopening comprises: forming a first cover layer on a side surface and thebottom of the opening; forming the pillar kernel filling the opening onthe first cover layer; forming a pillar cavity by etching back a portionof the pillar kernel; and forming a second cover layer filling thepillar cavity, wherein the first cover layer and the second cover layerform the common cover layer wrapped around the pillar kernel.
 17. Themethod of claim 14, wherein the pillar kernel is made of silicon dioxideand the common cover layer is made of undoped polycrystalline silicon.18. The method of claim 13, wherein the first sacrificial layers aremade of silicon nitride and the second sacrificial layers are made ofsilicon dioxide.
 19. The method of claim 13, wherein the channelstructure further comprises an anti-etching layer wrapped around thecharge capture layer.
 20. The method of claim 19, wherein theanti-etching layer is made of a High Temperature Oxide (HTO), whereinthe HTO is a silicon oxide formed in a temperature range from 300 to 500Celsius degree.